1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, particularly, to a delay locked loop circuit of a semiconductor device, and more particularly, to a delay locked loop circuit capable of adjusting clock-related specifications at a package level by itself.
2. Description of the Related Art
A synchronous semiconductor device, such as a double data rate synchronous DRAM (DDR SDRAM), transmits data to external devices using an internal clock synchronized with an external clock inputted from an external device such as a memory controller CTRL.
In order to stably transmit data between a memory and a memory controller a temporal synchronization between an external clock applied from the memory controller and data outputted from the memory is very important.
The memory outputs data in synchronization with an internal clock. The internal clock is synchronized with the external clock when it is initially applied to the memory, but the internal clock is delayed while passing through elements in the memory. Thus, the data is outputted to an exterior of the memory in a state in which it is not synchronized with the external clock.
In order to stably transmit data outputted from the memory, the internal clock, which has been delayed while passing through the elements in the memory for transmitting the data, should exactly match with the edge or center of the external clock applied from the memory controller. To this end, the internal clock should be synchronized with the external clock by reversely compensating for time for loading data on a bus.
A clock synchronization circuit for playing such a role includes a phase locked loop (PLL) circuit and a delay locked loop (DLL) circuit.
When frequencies of the external clock and the internal clock are different from each other, the phase locked loop (PLL) circuit is mainly used because a frequency multiplication function is needed. Meanwhile, when the frequencies of the external clock and the internal clock are substantially equal to each other, the delay locked loop (DLL) circuit is mainly used because it is not greatly affected by noise and may be implemented in a relatively small area, as compared with the phase locked loop (PLL) circuit.
That is since semiconductor memory elements commonly use substantially the same frequency, the delay locked loop (DLL) circuit is mainly used as the clock synchronization circuit.
FIG. 1 is a block diagram illustrating a delay locked loop (DLL) circuit of a general semiconductor device.
Referring to FIG. 1, the delay locked loop (DLL) circuit of the general semiconductor device includes a clock input buffering unit 10, a phase comparison unit 20, a variable delay unit 30, a delay replica model unit 40, and a clock output buffering unit 50. The clock input buffering unit 10 buffers an external clock EXT_CLK and generates an internal clock IN_CLK. The phase comparison unit 20 compares a phase of the internal clock IN_CLK with a phase of a feedback clock FB_CLK to generate a phase detection signal LOCK_DET according to a comparison result. The variable delay unit 30 delays the internal clock IN_CLK by a variable delay amount in response to the phase detection signal LOCK_DET, and outputs a delay locked clock DLLCLK. The delay replica model unit 40 delays the delay locked clock DLLCLK by a delay amount obtained by modeling a delay path of the internal clock IN_CLK in an internal circuit, and outputs the feedback clock FB_CLK. The clock output buffering unit 50 buffers the delay locked clock DLLCLK and outputs a data strobe signal DQS.
Meanwhile, a parameter indicating a time difference between the external clock EXT_CLK and the data strobe signal DQS includes a parameter ‘tDQSCK’. The most basic operation object of the delay locked loop (DLL) circuit is to synchronize data outputted from the semiconductor device with the external clock EXT_CLK by allowing the value of the parameter “tDQSCK” to be approximate to ‘0’ if possible.
In order to allow the value of the parameter ‘tDQSCK’ to be approximate to ‘0’ if possible, the most important factor is to model the delay amount, which is modeled by the delay replica model unit 40, to be approximate to an actual delay amount. That is, since the delay amount modeled by the delay replica model unit 40 is very large and has the most significant influence on a result of the delay locked loop (DLL) circuit, there should be no difference between the size of a delay amount modeled by the delay replica model unit 40 and corresponding to the delay path of the internal clock IN_CLK in the internal circuit and the size of an actual delay amount by which the internal clock IN_CLK is delayed in the internal circuit, in order to allow the value of the parameter ‘tDQSCK’ to be approximate to ‘0’ if possible.
However, since the delay replica model unit 40 simply models the delay amount corresponding to the delay path of the internal clock IN_CLK in the internal circuit, it is not possible to remove a difference between the size of the delay amount corresponding to the delay path of the internal clock IN_CLK in the internal circuit and the size of the actual delay amount during an actual operation. Particularly, when the delay amount of the delay replica model unit 40 is determined once in a design process, the determined delay amount is simultaneously applied to numerous semiconductor devices in mass production. Although the delay amount of the delay replica model unit 40 is exactly determined in a design process, there is a difference in the delay amount of the delay replica model unit 40, which is applied to respective semiconductor devices, due to various peripheral factors in mass production.
In order to solve such problems, in the conventional art, there has been used a method in which a fuse option and the like capable of adjusting the delay amount are put into the delay replica model unit 40, and the fuse option of the delay replica model unit 40 is adjusted for respective semiconductor devices through a ‘tDQSCK’ test in a process of performing a test operation for produced semiconductor devices, so that the delay amount of the delay replica model unit 40 is adjusted.
However, in the conventional method, much time is required for performing the test. That is, in the conventional method, since it is necessary to detect ‘tDQSCK’ values for the respective semiconductor devices and to adjust the fuse option of the delay replica model unit 40 included in the respective semiconductor devices based on the detected values, much time is required for performing the test.